As semiconductor fabrication technology advances, designers of integrated circuits and electronic circuits incorporating the same are able to integrate more and more functions into individual integrated circuit devices, or chips. As such, electronic designs that once required several integrated circuits electrically coupled to one another on a circuit board or module may now be integrated into fewer integrated circuits, thereby increasing performance and reducing cost.
With increases in circuit complexity, however, the processes of designing and testing circuit designs become increasingly complex and time consuming. As a result, computers have become increasingly important in automating the design and testing of circuit designs.
An important step in the development of a complex electronic system is that of verification, which is used to verify the functional operation of a circuit design. Traditionally, hardware circuit designs have been designed on a computer at a relatively high level of abstraction, typically in a hardware definition language such as VHDL or Verilog. Software tools, known as compilers, are then used to generate simulation models for the designs that can be executed on a logic simulator computer program to simulate the reactions of such circuit designs to various input conditions. By simulating the functional operation of a circuit design, potential errors or faulty logic can be identified and corrected in the high level design. Simulation is then rerun until the circuit design functions as desired.
However, with the increasingly complex nature of many circuit designs, software-based simulation is often too time consuming and inefficient. As a result, a significant amount of development effort has been directed toward hardware-based verification environments such as cycle simulators and logic emulators (hereinafter jointly referred to as “hardware-based emulators”). Both cycle simulation and logic emulation of a circuit design are often performed using a massively parallel hardware-based emulator incorporating hundreds or thousands of “emulation processors” that are used to emulate, in hardware, the various functional components of a circuit design. The emulation processors can be specifically designed to efficiently emulate various functional components, and thus permit the emulation of potentially millions of logic gates in substantially less time than would be required for software-based simulation.
Cycle simulation, for example, is used to verify the functionality of a circuit design by calculating the outputs of circuit components at clock edges, with typically only two logic states (binary 1 and 0) computed for each component output.
Related to cycle simulation is in-circuit logic emulation, which verifies the operation of a circuit design within an overall electronic system. For example, in-circuit logic emulation may be used to verify the proper interaction between a circuit design and a real-world target hardware system with which the eventually-manufactured product will operate. Moreover, in-circuit logic emulation may be used to verify a hardware circuit design running custom software, a process known as “coverification”. Thus, with in-circuit logic emulation, system-wide integration, testing and verification can be substantially simplified.
One exemplary type of hardware-based emulation environment is the ET3.5 emulation system from International Business Machines Corporation. The ET3.5 system includes potentially thousands of emulation processors distributed among multiple interconnected logic boards, with each logic board including sixty-five processor chips, and with each processor chip including sixty-four emulation processors. Emulation processors can individually emulate hundreds of logic gates, thereby permitting millions of logic gates to be emulated at any given time.
With a hardware-based emulator, a logic design to be emulated is typically in the form of a gate-level model that has been compiled from a high-level language. The compiled model breaks up each clock cycle (also referred to as an evaluation cycle) into a series of evaluation “steps”. The evaluation steps are typically executed in-order on each emulation processor, and are repeated during each evaluation cycle.
Given the highly parallel nature of most circuit designs, the ability to communicate information between emulation processors during logic emulation is often extremely important for accurately and efficiently verifying a logic design. To support such inter-processor communication in the ET3.5 system, for example, each processor chip is connected to a pair of connectors capable of interfacing the chip with other chips disposed on the same or different logic boards within the system. Each processor on the chip has a dedicated input pin (XBI) and output pin (XBO), and thus thirty-two processors use each connector. Processors are capable of reading and writing to their respective XBI/XBO pins during any evaluation step, and as a result, it is possible to time-multiplex multiple data signals between two chips using the XBI/XBO pins.
While the use of the aforementioned connectors between processor chips often provides adequate connectivity between processors, the interconnection mechanism is typically not capable of supporting asynchronous communications between processors with the same degree of connection density.
Asynchronous communications, for example, are required in a logic system whenever two electronic components are operating on different system clocks. All of the logic in a circuit design that operates under the same clock is typically referred to as a “clock domain.” Particularly in circuit designs incorporating multiple logic boards, as well as in designs that interface with target hardware systems, it is common for multiple clock domains to be utilized. While many logic emulators support the ability to emulate multiple clock domains, communicating signals between clock domains is problematic, since the receiver of an asynchronous signal has no clock relationship to the source, and thus cannot decode time-multiplexed data over a given signal path. As a result, conventional logic emulators have required that no more than one signal be communicated over a particular signal path between asynchronous clock domains. Otherwise, time-multiplexed signals could be misinterpreted and cause the generation of incorrect emulation results.
When only a few sets of signals are communicated between asynchronous clock domains in a circuit design, the limitation of one signal per signal path is not particularly burdensome. However, in many complex systems, thousands of signals may be required to be passed between asynchronous clock domains. With conventional logic emulators such as the aforementioned ET3.5 system, it has been found that tens or hundreds of cables may be required to communicate all necessary data between asynchronous clock domains. In many instances, these cables are very expensive, thus adding significant cost to a hardware-based emulation system. In addition, the more cables in a system, the more difficult the system is to administer, and the greater likelihood that a cable may fail or not be connected properly. Furthermore, connectivity limitations may decrease the number of logic gates that may be emulated in a given system, thus requiring a more complex, and thus more expensive, system to adequately emulate a particular design.
Therefore, a significant need continues to exist in the art for a manner of facilitating the communication of data signals between asynchronous clock domains in a hardware-based emulation environment. In particular, a need has existed for overcoming the limitation against time-multiplexing data across signal paths between asynchronous clock domains during emulation and/or simulation of a circuit design.